A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing

Authors:
Y. Tsiatouhas;A. Arapoyanni;D. Nikolos;Th. Haniotakis
Affiliations:
-;-;-;-
Venue:
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Year:
2002

Citing 0
Cited 3

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Abstract

Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the funtional circuit under check.