Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-line detection of logic errors due to crosstalk, delay, and transient faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Scaling Deeper to Submicron: On-Line Testing to the Rescue
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design for soft-error robustness to rescue deep submicron scaling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Concurrent Detection of Soft Errors Based on Current Monitoring
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Journal of Electronic Testing: Theory and Applications
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In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.