Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft delay error analysis in logic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA
Proceedings of the conference on Design, automation and test in Europe
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Switch-level soft error emulation for SET-induced pulses of variable strengths
Microelectronics Journal
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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Single event upsets (SEUs) are due to highenergetic particle strike at sensitive nodes of CMOScombinational circuits. In this paper, we introduce atype of soft errors which manifests as soft delay. Thesoft delay is temporary delay in CMOS combinationalcircuits due to high energetic particle strike. We describesoft delay model which enables us to examinedelay in CMOS combinational circuits due to particlestrike. As technology scales down, the delay due toparticle strike increases, and other factors such as V{dd}scaling, fanout and transistor strength also contributeto increase the soft delay in CMOS combinational circuits.