Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Fault Grading FPGA Interconnect Test Configurations
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft Delay Error Effects in CMOS Combinational Circuits
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
Proceedings of the 41st annual Design Automation Conference
Soft Error Mitigation for SRAM-Based FPGAs
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
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Soft errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft error tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft error tolerance results are presented and compared with standard SRAM cell and an existing increased soft error tolerance cell. Simulation results show that our cell has lowest soft error rate at the various supply voltages.