Soft Error Mitigation for SRAM-Based FPGAs

Authors:
Ghazanfar-Hossein Asadi;Mehdi Baradaran Tahoori
Affiliations:
Northeastern University;Northeastern University
Venue:
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Year:
2005

Citing 0
Cited 6

Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA

Proceedings of the conference on Design, automation and test in Europe
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs

Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes

Microelectronics Journal

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Abstract

FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits. In this paper, we present a high-reliable low-cost mitigation technique which can significantly improve the availability of designs mapped into FPGAs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increases to more than 99%.