Accelerated testing for cosmic soft-error rate
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
A memory coherence technique for online transient error recovery of FPGA configurations
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Soft error rate estimation and mitigation for SRAM-based FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Soft Error Mitigation for SRAM-Based FPGAs
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Efficient Estimation of SEU Effects in SRAM-Based FPGAs
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An analytical method for reliability aware instruction set extension
The Journal of Supercomputing
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
Journal of Electronic Testing: Theory and Applications
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Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.