Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A multilevel fault model for integrated parallel fault-tolerant systems
Concurrency and Computation: Practice & Experience
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
Journal of Electronic Testing: Theory and Applications
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SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to Single Event Upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAsý configuration memory. In this paper we propose a new method for assessing the impact of faults in the configuration memory on the FPGA dependability. The method uses static analysis, thus reducing greatly the time for performing dependability evaluation.