Terrestrial cosmic ray intensities
IBM Journal of Research and Development
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Efficient Estimation of SEU Effects in SRAM-Based FPGAs
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Single Event Upset: An Embedded Tutorial
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs
DFT '12 Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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The goal of this work is to develop a methodical approach for analytical soft error sensitivity analysis in SRAM-based FPGAs. Compared to other non-destructive techniques, the proposed approach can be applied very early in a design flow. This is achieved by extracting information about an application under development from high level models (e.g. C/C++ descriptions or Matlab Simulink models) and then invoking pre-established libraries where other information related to soft error sensitivity of primitive components are stored beforehand. Our library-based approach is validated by comparing our early estimation results to those obtained through synthesis, placement and routing of complete designs, for two different ways of estimating the number of potentially critical configuration bits. We first explore two different design architectures for implementing Finite Impulse Response filters. The design architectures are explored under two different implementation options, for a Xilinx Virtex-5 FPGA: LUT based and DSP48E block based. Then we apply our estimation technique on a more complex design. namely a GMSK demodulator. Results show that the worst case relative error, caused by our estimation technique with respect to the results obtained after synthesis, placement and routing is 7,2聽%, and in most cases, it is less than 5聽%. Mean time between failures are provided for the different design architecture and implementation options, to illustrate how our technique can help designers make early choices to build more reliable designs without performing the whole implementation, as our early estimation results are close to those obtained later in the design process.