Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs

Authors:
Luca Cassano
Affiliations:
Department of Information Engineering, University of Pisa, Italy
Venue:
DFT '12 Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Year:
2012

Citing 0
Cited 2

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design

Journal of Electronic Testing: Theory and Applications

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Abstract

SRAM-based FPGAs are more and more relevant in a growing number of applications, ranging from the automotive to the aerospace ones. Designers of safety-critical applications demand accurate methodologies to evaluate the Single Event Upsets (SEUs) sensitivity of their designs. In this paper, we present an accurate simulation method for the evaluation of the effects of SEUs in the configuration memory of SRAM-based FPGAs. The approach is able to simulate SEUs affecting the configuration memory of both logic and routing resources since it is able to accurately model the electrical behavior of SEUs in the configuration memory. Detailed experimental results on a large set of benchmark circuits are provided and the comparison with fault injection experiments is shown in order to validate the accuracy of the proposed method. The results clearly demonstrate the benefits of our approach since simulation results predict almost completely the results obtained through fault injection.