FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A New Functional Fault Model for FPGA Application-Oriented Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Hierarchical Identification of Untestable Faults in Sequential Circuits
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Untestable Fault Identification in Sequential Circuits Using Model-Checking
ATS '08 Proceedings of the 2008 17th Asian Test Symposium
A fast untestability proof for SAT-based ATPG
DDECS '09 Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits
ETS '11 Proceedings of the 2011 Sixteenth IEEE European Test Symposium
Survey: Linear Temporal Logic Symbolic Model Checking
Computer Science Review
SEU-X: A SEu un-excitability prover for SRAM-FPGAs
IOLTS '12 Proceedings of the 2012 IEEE 18th International On-Line Testing Symposium (IOLTS 2012)
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs
DFT '12 Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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Testing SEUs in the configuration memory of SRAM-based FPGAs is very costly due to their large configuration memory, therefore it is necessary to optimize the generation of test patterns. In particular, in order to reduce the effort required of automatic test pattern generators, it is useful to identify early the unexcitable faults, i.e., those faults that cannot be excited by any combination of input signals. In this paper, the unexcitability of SEUs affecting the configuration bits controlling the routing resources of SRAM-based FPGAs is considered. Since this part of the configuration memory contains the largest number of configuration bits, its testing is particularly onerous. Faults in the routing resources are modeled considering the actual electrical behavior of the affected interconnections, thus the resulting fault model is more accurate than the classical open/short model usually considered. This paper introduces a methodology to prove the unexcitability of these faults. The methodology has been implemented in a tool based on a formal specification language (SAL) and a model checker (SAL-SMC). Results from the application of the tool to some circuits from the ITC'99 benchmark are reported.