Hierarchical Identification of Untestable Faults in Sequential Circuits

Authors:
Jaan Raik;Raimund Ubar;Anna Krivenko;Margus Kruus
Affiliations:
Tallinn University of Technology;Tallinn University of Technology;Tallinn University of Technology;Tallinn University of Technology
Venue:
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Year:
2007

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Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

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Abstract

Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability identification operate at the logic-level and, thus, the methods do not scale. Current paper points out a new class of sequentially untestable faults, called register input logic stuck-on faults. We show that it is possible to identify such faults from the registertransfer level (RTL) description of the circuit. Moreover, we prove by experiments that the considered faults form a large subclass of all the untested faults.