Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verification of synchronous sequential machines based on symbolic execution
Proceedings of the international workshop on Automatic verification methods for finite state systems
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Algorithms for approximate FSM traversal
DAC '93 Proceedings of the 30th international Design Automation Conference
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On redundancy and untestability in sequential circuits
On redundancy and untestability in sequential circuits
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Simulation-Based Engineering for Industrial Competitive Advantage
IEEE Design & Test
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Latch Redundancy Removal Without Global Reset
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
One-Pass Redundancy Identification and Removal
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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In this paper, we first present an algorithm (FILL) to efficiently identify a large subset of illegal states in synchronous sequential circuits, without assuming a global reset mechanism. A second algorithm, FUNI, finds sequentially untestable faults whose detection requires some of the illegal states computed by FILL. Although based on binary decision diagrams (BDDs), FILL is able to process large circuits by using a new functional partitioning procedure. The incremental building of the set of illegal states guarantees that FILL will always obtain at least a partial solution. FUNI is a direct method that identifies untestable faults without using the exhaustive search involved in automatic test generation (ATG). Experimental results show that FUNI finds a large number of untestable faults up to several orders of magnitude faster than an ATG algorithm that targeted the faults identified by FUNI. Also, many untestable faults identified by FUNI were aborted by the test generator.