On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On redundancy and untestability in sequential circuits
On redundancy and untestability in sequential circuits
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Sequential Redundancy Identification Using Verification Techniques
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Is IDDQ Yield Loss Inevitable?
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sequential redundancy identification using recursive learning
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
The case for retiming with explicit reset circuitry
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential optimisation without state space exploration
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data driven power optimization of sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Efficient Identification of Non-Robustly Untestable Path Delay Faults
ITC '97 Proceedings of the 1997 IEEE International Test Conference
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Untestable fault identification through enhanced necessary value assignments
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Functional broadside tests under an expanded definition of functional operation conditions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integration, the VLSI Journal
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Combinational techniques for sequential equivalence checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing: Theory and Applications
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