Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic test knowledge extraction from VHDL (ATKET)
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
GRASP—a new search algorithm for satisfiability
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Fast identification of untestable delay faults using implications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
Static logic implication with application to redundancy identification
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Maximizing Impossibilities for Untestable Fault Identification
Proceedings of the conference on Design, automation and test in Europe
BerkMin: A Fast and Robust Sat-Solver
Proceedings of the conference on Design, automation and test in Europe
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Proceedings of the 41st annual Design Automation Conference
SATORI - A Fast Sequential SAT Engine for Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Pseudo-Functional Scan-based BIST for Delay Fault
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An Approach to Minimizing Functional Constraints
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Checking the play in plug-and-play
IEEE Spectrum
Identifying invalid states for sequential circuit test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New techniques for untestable fault identification in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational ATPG theorems for identifying untestable faults in sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Functional constraints capture Boolean relationships among signal nets by analyzing the functionality of a circuit. Such constraints find widespread application in VLSI design methodology and can be derived using various techniques. The size and complexity of these constraints becomes a limiting factor in their successful usage for large designs. This paper describes CONAN (Constraint Analyzer), a powerful framework to analyze and simplify such constraints. CONAN is built on the solution to a novel minimization problem. The feasibility and effectiveness of CONAN is demonstrated by using it for functional untestability analysis of large industrial benchmarks. Run-times were reduced from over a week to less than 30 minutes. Additionally, unique functionally untestable faults were derived using this approach when compared with constraints provided by designers.