Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
Journal of Electronic Testing: Theory and Applications
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We describe a time-efficient procedure for identifying undetectable and redundant faults in a synchronous sequential circuit, without using a sequential circuit test pattern generator. The proposed procedure is based on the use of a limited length iterative logic array model of the circuit, and has two phases. In the first phase, faults that will not be proved to be undetectable are identified. In the second phase, undetectable faults are identified out of the remaining faults using a combinational circuit test generator. Sequential static learning on the fault-free circuit and a subset of unreachable states are used in the proposed procedure to increase the amount of information available when considering an iterative logic array model of limited length. An undetectable fault in a synchronizable circuit that leaves the faulty circuit synchronizable is identified as a redundant fault. Experimental results presented in this work demonstrate the effectiveness of the proposed techniques in finding undetectable and redundant faults. Larger numbers of undetectable and redundant faults are found compared to earlier works.Keywork : test generation, undetectable faults, redundant faults, synchronous sequential circuit