DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Proceedings of the IEEE International Test Conference 2001
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On improving genetic optimization based test generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
A new test pattern generation method for delay fault testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
MUST: Multiple-Stem Analysis for Identifying Sequentially Untestable Faults
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Identifying sequentially untestable faults using illegal states
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Constraint extraction for pseudo-functional scan-based delay testing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We investigate a complementary view whereby the goal is to avoid the assignment of certain input values in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Other potential uses of the computed input cubes are in a deterministic test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults. We consider stuck-at faults in full-scan circuits. We also extend the discussion to four-way bridging faults.