CRIS: a test cultivation program for sequential VLSI circuits

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits

Journal of Electronic Testing: Theory and Applications

Using Non-uniform Crossover in Genetic Algorithm Methods to Speed up the Generation of Test Patterns for Sequential Circuits

SETN '02 Proceedings of the Second Hellenic Conference on AI: Methods and Applications of Artificial Intelligence

Native mode functional test generation for processors with applications to self test and design validation

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Alternating Strategies for Sequential Circuit ATPG

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Advanced Techniques for GA-based sequential ATPGs

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation

VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications

EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

LOCSTEP: A Logic Simulation-Based Test Generation Procedure

FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing

Evolutionary algorithms for the physical design of VLSI circuits

Advances in evolutionary computing

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?

HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop

On modeling and testing of lithography related open faults in nano-CMOS circuits

Proceedings of the conference on Design, automation and test in Europe

Dynamic test compaction for a random test generation procedure with input cube avoidance

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

TOV: sequential test generation by ordering of test vectors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

On test generation with test vector improvement

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Reducing the storage requirements of a test sequence by using a background vector

Proceedings of the Conference on Design, Automation and Test in Europe

An automatic test pattern generator for large sequential circuits based on genetic algorithms

ITC'94 Proceedings of the 1994 international conference on Test

Challenges in fault detection

FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing

Random test generation with input cube avoidance

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs

Journal of Systems Architecture: the EUROMICRO Journal