The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
On Fault Simulation for Synchronous Sequential Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Time-efficient automatic test pattern generation systems
Time-efficient automatic test pattern generation systems
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Full-Symbolic ATPG for Large Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Improved sequential ATPG using functional observation information and new justification methods
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Automatic test generation using genetically-engineered distinguishing sequences
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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We describe an approach to test generation for synchronous sequential circuits that accepts a given test sequence T and targets only faults that could not be detected by the test generation procedure that produced T (hard to detect faults). For every fault f that remains undetected by T, the proposed procedure extracts from T a small number of subsequences (two or three subsequences) that can be combined to form a test sequence for f. It then adds these sequences, if found, to T. By exploring only test sequences that can be extracted from T, a restricted search space for test generation is obtained, and it can be thoroughly explored. Experimental results show that non-trivial numbers of additional faults can be detected by using the proposed procedure to extend a given test sequence T.