Logic testing and design for testability
Logic testing and design for testability
Differential fault simulation - a fast method using minimal memory
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Fault simulation under the multiple observation time approach using backward implications
DAC '97 Proceedings of the 34th annual Design Automation Conference
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate-level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.Index Terms驴Fault simulation, Multiple observation time test strategy, Single observation time test strategy, Synchronous sequential circuits, Three-value logic.