Logic testing and design for testability
Logic testing and design for testability
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
IEEE Transactions on Computers - The MIT Press scientific computation series
A protocol test generation procedure
Computer Networks and ISDN Systems
Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
On removing redundancy in sequential circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
RTG: automatic register level test generator
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
EBT: A comprehensive test generation technique for highly sequential circuits
DAC '78 Proceedings of the 15th Design Automation Conference
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
On improving fault diagnosis for synchronous sequential circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
On Fault Simulation for Synchronous Sequential Circuits
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The validity of retiming sequential circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Exploiting power-up delay for sequential optimization
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
IEEE Transactions on Computers
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Identifying sequential redundancies without search
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of Sequential Circuits by Redundancy Removal and Retiming
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Full scan fault coverage with partial scan
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits
IEEE Transactions on Computers
Isomorph-Redundancy in Sequential Circuits
IEEE Transactions on Computers
Application of Homing Sequences to Synchronous Sequential Circuit Testing
IEEE Transactions on Computers
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
IEEE Transactions on Computers
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Sequential optimization in the absence of global reset
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On undetectable faults in partial scan circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Testable design of non-scan sequential circuits using extra logic
ATS '95 Proceedings of the 4th Asian Test Symposium
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Does retiming affect redundancy in sequential circuits?
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
On Full Reset as a Design-For-Testability Technique
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Characterization and Implicit Identification of Sequential Indistinguishability
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
8.4 Undetectable Fault Removal of Sequential Circuits Based on Unreachable States
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
8.3 On Removing Redundant Faults in Synchronous Sequential Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Synthesis for Testability by Sequential Redundancy Removal Using Retiming
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Application of Tools Developed at the University of Iowa to ITC-99 Benchmarks
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
ITC'94 Proceedings of the 1994 international conference on Test
On achieving complete testability of synchronous sequential circuits with synchronizing sequences
ITC'94 Proceedings of the 1994 international conference on Test
| Hi-index | 15.00 |
Undetectable and redundant faults in synchronous sequential circuits are analyzed. A distinction is drawn between undetectable faults and faults that are never manifested as output errors. The latter are classified as redundant. It is shown that there are faults for which a test sequence does not exist; however, under certain initial conditions (or initial states) of the circuit, faulty behavior may be observed. Such faults are called partially detectable faults. A partially detectable fault is undetectable, but is not redundant, as it affects circuit operation under some conditions. The author observes that the notion of redundancy cannot be separated from the mode of operation of the circuit. Two modes of operation are considered, representative of common modes, called the synchronization mode and the free mode. Accordingly, the identification of redundant faults calls for different test generation strategies. Two test strategies to generate tests for detectable faults and partial tests for partially detectable faults are defined, called the restricted test strategy and the unrestricted test strategy.