On the over-specification problem in sequential ATPG algorithms
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Initializability Consideration in Sequential Machine Synthesis
IEEE Transactions on Computers
The Multiple Observation Time Test Strategy
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Symbolic Model Checking
Classification of Faults in Synchronous Sequential Circuits
IEEE Transactions on Computers
Proceedings of the 8th International Conference on Computer Aided Verification
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Model Checking of Safety Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
PVS: Combining Specification, Proof Checking, and Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verification Tools for Finite-State Concurrent Systems
A Decade of Concurrency, Reflections and Perspectives, REX School/Symposium
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Approach to Verify a Large Scale System-on-a-chip Using Symbolic Model Checking
ICCD '98 Proceedings of the International Conference on Computer Design
State information-based solutions for sequential circuit diagnosis and testing
State information-based solutions for sequential circuit diagnosis and testing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
Semi-formal Bounded Model Checking
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automated Test Generation and Verified Software
Verified Software: Theories, Tools, Experiments
Synchronizing Automata and the Černý Conjecture
Language and Automata Theory and Applications
EverLost: a flexible platform for industrial-strength abstraction-guided simulation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Test compaction techniques for assertion-based test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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State-space explosion remains to be a significant challenge for Finite State Machine (FSM) exploration techniques in model checking and sequential verification. In this work, we study the use of sequential ATPG (Automatic Test-Pattern Generation) as a solution to overcome the problem for a useful class of temporal logic properties. We also develop techniques to exploit the existence of synchronizing sequences to reduce some temporal logic properties to simpler properties that can be efficiently checked using an ATPG algorithm. We show that the method has the potential to scale up to large, industrial-strength, hardware designs for which current model checking techniques fail.