Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Sequential circuit verification using symbolic model checking
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Representing circuits more efficiently in symbolic model checking
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Efficient generation of counterexamples and witnesses in symbolic model checking
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Symbolic Model Checking
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Forward model checking techniques oriented to buggy designs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Approximate reachability don't cares for CTL model checking
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Symbolic guided search for CTL model checking
Proceedings of the 37th Annual Design Automation Conference
Formal verification based on assume and guarantee approach — a case study (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Optimizing Symbolic Model Checking for Statecharts
IEEE Transactions on Software Engineering - Special issue on 1999 international conference on software engineering
ICSE '01 Proceedings of the 23rd International Conference on Software Engineering
Formal Methods in System Design
Multiple State and Single State Tableaux for Combining Local and Global Model Checking
Correct System Design, Recent Insight and Advances, (to Hans Langmaack on the occasion of his retirement from his professorship at the University of Kiel)
Hints to accelerate Symbolic Traversal
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Improving Symbolic Model Checking by Rewriting Temporal Logic Formulae
RTA '02 Proceedings of the 13th International Conference on Rewriting Techniques and Applications
Symbolic Model Checking with Fewer Fixpoint Computations
FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume I - Volume I
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Model Checking Based on Sequential ATPG
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
From Pre-Historic to Post-Modern Symbolic Model Checking
Formal Methods in System Design
A tutorial introduction to symbolic model checking
Logic for concurrency and synchronisation
Accelerating Bounded Model Checking of Safety Properties
Formal Methods in System Design
Forward symbolic model checking for real time systems
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Verification Techniques for System-Level Design
Verification Techniques for System-Level Design
Combining partial-order reduction and symbolic model checking to verify LTL properties
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Milestones: a model checker combining symbolic model checking and partial order reduction
NFM'11 Proceedings of the Third international conference on NASA Formal methods
BDD-Based hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Distributed explicit state model checking of deadlock freedom
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We present a CTL model checking algorithm based mainly on forward state traversal, which can check many realistic CTL properties without doing backward state traversal. This algorithm is effective in many situations where backward state traversal is more expensive than forward state traversal. We combine it with BDD-based state traversal techniques using partitioned transition relations. Experimental results show that our method can verify actual CTL properties of large industrial models which cannot be handled by conventional model checkers.