Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
RuleBase: an industry-oriented formal verification tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
CTL model checking based on forward state traversal
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Improving efficiency of symbolic model checking for state-based system requirements
Proceedings of the 1998 ACM SIGSOFT international symposium on Software testing and analysis
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Efficient Detection of Vacuity in Temporal Model Checking
Formal Methods in System Design - Special issue on CAV '97
On the Effective Deployment of Functional Formal Verification
Formal Methods in System Design
Comparing Symbolic and Explicit Model Checking of a Software System
Proceedings of the 9th International SPIN Workshop on Model Checking of Software
Characterizing Correctness Properties of Parallel Programs Using Fixpoints
Proceedings of the 7th Colloquium on Automata, Languages and Programming
Scalable Distributed On-the-Fly Symbolic Model Checking
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Specification and verification of concurrent systems in CESAR
Proceedings of the 5th Colloquium on International Symposium on Programming
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Tuning SAT Checkers for Bounded Model Checking
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Stochastic Colored Petri Net Models for Rainbow Optical Networks
Application of Petri Nets to Communication Networks, Advances in Petri Nets
Efficient Model Checking by Automated Ordering of Transition Relation Partitions
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Efficient Detection of Vacuity in ACTL Formulas
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
RuleBase: Model Checking at IBM
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
MDG-based Verification by Retiming and Combinational Transformations
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Formal verification: is it real enough?
Proceedings of the 42nd annual Design Automation Conference
Challenges in the Formal Verification of Complete State-of-the-Art Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
Explaining Counterexamples Using Causality
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Supporting SAT based BMC on Finite Path Models
Electronic Notes in Theoretical Computer Science (ENTCS)
Formal verification of arbiters using property strengthening and underapproximations
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems
IBM Journal of Research and Development
An improved case-based approach to LTL model checking
RISE'05 Proceedings of the Second international conference on Rapid Integration of Software Engineering Techniques
A case study: formal verification of processor critical properties
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Explaining counterexamples using causality
Formal Methods in System Design
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Over the past nine years, the Formal Methods Group at the IBM Haifa Research Laboratory has made steady progress in developing tools and techniques that make the power of model checking accessible to the community of hardware designers and verification engineers, to the point where it has become an integral part of the design cycle of many teams. We discuss our approach to the problem of integrating formal methods into an industrial design cycle, and point out those techniques which we have found to be especially effective in an industrial setting.