On the Effective Deployment of Functional Formal Verification
Formal Methods in System Design
Formal Models for Embedded System Design
IEEE Design & Test
Specification of real-time and hybrid systems in rewriting logic
Theoretical Computer Science - Rewriting logic and its applications
Formal Methods in System Design
On-the-Fly Model Checking of RCTL Formulas
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Checking formal specifications under simulation
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Monitoring Programs Using Rewriting
Proceedings of the 16th IEEE international conference on Automated software engineering
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Writing Testbenches: Functional Verification of HDL Models, Second Edition
Computer Organization and Design
Computer Organization and Design
The rewriting logic semantics project
Theoretical Computer Science
A rewriting logic approach to operational semantics
Information and Computation
The rewriting logic semantics project: a progress report
FCT'11 Proceedings of the 18th international conference on Fundamentals of computation theory
The rewriting logic semantics project: A progress report
Information and Computation
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We present a rewriting logic semantics in Maude of the ABEL hardware description language. Based on this semantics, and on Maude's underlying LTL model checker, we propose a scalable formal analysis framework and tool for hardware/software co-design. The analysis method is based on trace checking of finite system behaviors against LTL temporal logic formulas. The formal properties of the hardware, the embedded software, and the interactions between both can all be analyzed this way. We present two case studies illustrating our method and tool.