An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Model Checking of Safety Properties
Formal Methods in System Design
Formal Methods in System Design
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Improvements in Coverability Analysis
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cross-Product Functional Coverage Measurement with Temporal Properties-Based Assertions
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Automated Synthesis of Assertion Monitors using Visual Specifications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Combining System Level Modeling with Assertion Based Verification
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Functional Verification of Networked Embedded Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Supporting sequential assumptions in hybrid verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Complementary use of runtime validation and model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Properties Incompleteness Evaluation by Functional Verification
IEEE Transactions on Computers
Incremental ABV for functional validation of TL-to-RTL design refinement
Proceedings of the conference on Design, automation and test in Europe
A Rewriting Semantics for ABEL with Applications to Hardware/Software Co-Design and Analysis
Electronic Notes in Theoretical Computer Science (ENTCS)
System on Chips optimization using ABV and automatic generation of SystemC codes
Microprocessors & Microsystems
Automata-based assertion-checker synthesis of PSL properties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Too Few or Too Many Properties? Measure it by ATPG!
Journal of Electronic Testing: Theory and Applications
Engineering of An Assertion-based PSLSimple-Verilog Dynamic Verifier by Alternating Automata
Electronic Notes in Theoretical Computer Science (ENTCS)
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Embedding finite automata within regular expressions
Theoretical Computer Science
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Applied Assertion-Based Verification: An Industry Perspective
Foundations and Trends in Electronic Design Automation
An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
Computers and Electrical Engineering
The role of mutation analysis for property qualification
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Diagnosis of faults in template-based asynchronous circuits
SOC'09 Proceedings of the 11th international conference on System-on-chip
AMT: a property-based monitoring tool for analog systems
FORMATS'07 Proceedings of the 5th international conference on Formal modeling and analysis of timed systems
PSL for runtime verification: theory and practice
RV'07 Proceedings of the 7th international conference on Runtime verification
Reactivity in systemC transaction-level models
HVC'07 Proceedings of the 3rd international Haifa verification conference on Hardware and software: verification and testing
Transaction-based debugging of system-on-chips with patterns
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Checking temporal properties of discrete, timed and continuous behaviors
Pillars of computer science
A cost effective approach for online error detection using invariant relationships
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analog property checkers: a DDR2 case study
Formal Methods in System Design
Validating assertion language rewrite rules and semantics with automated theorem provers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Vacuity analysis for property qualification by mutation of checkers
Proceedings of the Conference on Design, Automation and Test in Europe
Detecting errors using multi-cycle invariance information
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized temporal monitors for SystemC
RV'10 Proceedings of the First international conference on Runtime verification
Model-driven design and validation of embedded software
Proceedings of the 6th International Workshop on Automation of Software Test
Experimental evaluation of classical automata constructions
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Hardware design and simulation for verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Deterministic dynamic monitors for linear-time assertions
FATES'06/RV'06 Proceedings of the First combined international conference on Formal Approaches to Software Testing and Runtime Verification
A case for runtime validation of hardware
HVC'05 Proceedings of the First Haifa international conference on Hardware and Software Verification and Testing
Runtime verification: a computer architecture perspective
RV'11 Proceedings of the Second international conference on Runtime verification
Abstract property language for MDG model checking methodology
International Journal of Computer Applications in Technology
Optimized temporal monitors for SystemC
Formal Methods in System Design
On-Line detection and prediction of temporal patterns
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Approximating checkers for simulation acceleration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Enabling dynamic assertion-based verification of embedded software through model-driven design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems and Software
Proceedings of the International Conference on Computer-Aided Design
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