Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Memory-efficient algorithms for the verification of temporal properties
Formal Methods in System Design - Special issue on computer-aided verification: general methods
Reasoning about infinite computations
Information and Computation
A methodology for the verification of a “system on chip”
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
System Design with SystemC
Model Checking of Safety Properties
Formal Methods in System Design
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
Assertion-based verification turns the corner
IEEE Design & Test
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automata-Based Verification of Temporal Properties on Running Programs
Proceedings of the 16th IEEE international conference on Automated software engineering
Checking Finite Traces Using Alternating Automata
Formal Methods in System Design
SPOT: An Extensible Model Checking Library Using Transition-Based Generalized Büchi Automata
MASCOTS '04 Proceedings of the The IEEE Computer Society's 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
Proven correct monitors from PSL specifications
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Tractable and Fast Method for Monitoring SystemC TLM Specifications
IEEE Transactions on Computers
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Engineering A Compiler
Temporal Assertions using AspectJ
Electronic Notes in Theoretical Computer Science (ENTCS)
Proceedings of the 14th international SPIN conference on Model checking software
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Monitoring of real-time properties
FSTTCS'06 Proceedings of the 26th international conference on Foundations of Software Technology and Theoretical Computer Science
Experimental evaluation of classical automata constructions
LPAR'05 Proceedings of the 12th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Efficient monitoring of ω-languages
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
On the construction of fine automata for safety properties
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Deterministic dynamic monitors for linear-time assertions
FATES'06/RV'06 Proceedings of the First combined international conference on Formal Approaches to Software Testing and Runtime Verification
Larger automata and less work for LTL model checking
SPIN'06 Proceedings of the 13th international conference on Model Checking Software
Automatic aspectization of systemC
Proceedings of the 2012 workshop on Modularity in Systems Software
Enabling dynamic assertion-based verification of embedded software through model-driven design
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
LTL translation improvements in Spot 1.0
International Journal of Critical Computer-Based Systems
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SystemC is a modeling language built as an extension of C++. Its growing popularity and the increasing complexity of designs have motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV), where the designer asserts properties that capture the design intent in a formal language such as PSL or SVA. The model then can be verified against the properties using runtime or formal verification techniques. In this paper we focus on automated generation of runtime monitors from temporal properties. Our focus is on minimizing runtime overhead, rather than monitor size or monitor-generation time. We identify four issues in monitor generation: state minimization, alphabet representation, alphabet minimization, and monitor encoding. We conduct extensive experimentation on a synthetic workload and identify a configuration that offers the best performance in terms of runtime overhead.