A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Formal semantics for PSL modeling layer and application to the verification of transactional models
Proceedings of the Conference on Design, Automation and Test in Europe
Optimized temporal monitors for SystemC
RV'10 Proceedings of the First international conference on Runtime verification
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Runtime verification of typical requirements for a space critical SoC patform
FMICS'11 Proceedings of the 16th international conference on Formal methods for industrial critical systems
Optimized temporal monitors for SystemC
Formal Methods in System Design
Automatic refinement of requirements for verification throughout the SoC design flow
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Diagnosing root causes of system level performance violations
Proceedings of the International Conference on Computer-Aided Design
Automatic Generation of System Level Assertions from Transaction Level Models
Journal of Electronic Testing: Theory and Applications
| Hi-index | 14.98 |
The TLM modeling level of the SystemC language emphasizes the transactions in a complex system, considered at a very high level of abstraction. This level of specification considerably improves simulation performance and is therefore increasingly being adopted. We address assertion-based verification (ABV) of TLM SystemC models. We propose a framework for supervising during simulation the verification of temporal properties expressed in PSL. Very few modifications are needed in the original SystemC code. The TLM specification can be timed or not. The properties can involve several channels, of different types.