Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Interactive presentation: Implementation of a transaction level assertion framework in SystemC
Proceedings of the conference on Design, automation and test in Europe
A Tractable and Fast Method for Monitoring SystemC TLM Specifications
IEEE Transactions on Computers
Formal semantics for PSL modeling layer and application to the verification of transactional models
Proceedings of the Conference on Design, Automation and Test in Europe
Design and verification of systemc transaction-level models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
SystemC TLM (Transaction Level Modeling) enables the description of complex Systems on Chip (SoC) at a high level of abstraction. It offers a number of advantages regarding architecture exploration, simulation performance, and early software development. The tendency is therefore to use TLM-based descriptions of SoC platforms as golden models that, by essence, must be flawless. In this paper, a SoC critical embedded platform under development by Astrium is used as proof-of-concept demonstrator, to assess the ISIS prototype tool which is devoted to the verification of SystemC TLM designs. Given temporal properties that capture the intended requirements, ISIS automatically instruments the design with ad hoc checkers that inform about the satisfaction of the properties during simulation. After a description of the target platform design, we show that the PSL language enables the unambiguous expression of the required properties, and that the checkers produced by ISIS verify their satisfaction with a limited simulation time overhead.