Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Handbook of theoretical computer science (vol. B)
Reasoning about infinite computations
Information and Computation
An automata-theoretic approach to linear temporal logic
Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency : structure versus automata: structure versus automata
Journal of the ACM (JACM)
Model checking
Principles of Verifiable RTL Design
Principles of Verifiable RTL Design
Model Checking of Safety Properties
Formal Methods in System Design
Introduction To Automata Theory, Languages, And Computation
Introduction To Automata Theory, Languages, And Computation
The ForSpec Temporal Logic: A New Temporal Property-Specification Language
TACAS '02 Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems
CONCUR '00 Proceedings of the 11th International Conference on Concurrency Theory
Improved Automata Generation for Linear Temporal Logic
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Efficient Büchi Automata from LTL Formulae
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Benefits of Bounded Model Checking at an Industrial Setting
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automata-Based Verification of Temporal Properties on Running Programs
Proceedings of the 16th IEEE international conference on Automated software engineering
Incorporating Ef.cient Assertion Checkers into Hardware Emulation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
Efficient LTL compilation for SAT-based model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Verification Methodology Manual for SystemVerilog
Verification Methodology Manual for SystemVerilog
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Resets vs. aborts in linear temporal logic
TACAS'03 Proceedings of the 9th international conference on Tools and algorithms for the construction and analysis of systems
Efficient model checking of safety properties
SPIN'03 Proceedings of the 10th international conference on Model checking software
Efficient monitoring of ω-languages
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
LTL Path Checking Is Efficiently Parallelizable
ICALP '09 Proceedings of the 36th Internatilonal Collogquium on Automata, Languages and Programming: Part II
Automata-theoretic model checking revisited
VMCAI'07 Proceedings of the 8th international conference on Verification, model checking, and abstract interpretation
Validating assertion language rewrite rules and semantics with automated theorem provers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized temporal monitors for SystemC
RV'10 Proceedings of the First international conference on Runtime verification
On the construction of fine automata for safety properties
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
Optimized temporal monitors for SystemC
Formal Methods in System Design
| Hi-index | 0.00 |
We describe a framework for dynamic verification of temporal assertions based on assertion compilation into deterministic automata. The novelty of our approach is that it allows efficient dynamic verification of general linear temporal formulas written in formal property specification languages such as LTL, ForSpec, PSL, and SVA, while the existing approaches are applicable to limited subsets only. We also show an advantage of the described framework over industrial simulators, which typically use transaction-based verification. Another advantage of our approach is its ability to use deterministic checkers directly for hardware emulation. Finally, we compare the deterministic compilation with the OBDD-based on-the-fly simulation of deterministic automata. We show that although the OBDD-based simulation method is much slower, the two methods may be efficiently combined for hybrid simulation, when the RTL signals in assertions are mixed with symbolic variables.