The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Functional verification methodology for the PowerPC 604 microprocessor
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Model checking
A static analyzer for finding dynamic programming errors
Software—Practice & Experience
Symbolic execution and program testing
Communications of the ACM
The simulation semantics of systemC
Proceedings of the conference on Design, automation and test in Europe
System Design with SystemC
System Design: A Practical Guide with Specc
System Design: A Practical Guide with Specc
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Verifying the FM9801 Microarchitecture
IEEE Micro
Modeling and Verification of Out-of-Order Microprocessors in UCLID
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Counterexample-Guided Abstraction Refinement
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
PVS: A Prototype Verification System
CADE-11 Proceedings of the 11th International Conference on Automated Deduction: Automated Deduction
Reachability Analysis for Formal Verification of SystemC
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Assertion-Based Design
An overview of JML tools and applications
International Journal on Software Tools for Technology Transfer (STTT) - Special section on formal methods for industrial critical systems
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling
SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
A Practical Introduction to PSL (Series on Integrated Circuits and Systems)
Deterministic dynamic monitors for linear-time assertions
FATES'06/RV'06 Proceedings of the First combined international conference on Formal Approaches to Software Testing and Runtime Verification
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
Predictive runtime verification of multi-processor SoCs in SystemC
Proceedings of the 45th annual Design Automation Conference
Race analysis for SystemC using model checking
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A temporal language for SystemC
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
SystemC/C-based model-driven design for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Shortening the verification cycle with synthesizable abstract models
Proceedings of the 46th Annual Design Automation Conference
Full simulation coverage for SystemC transaction-level models of systems-on-a-chip
Formal Methods in System Design
Race analysis for systemc using model checking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SC-DEVS: an efficient SystemC extension for the DEVS model of computation
Proceedings of the Conference on Design, Automation and Test in Europe
Sysfier: Actor-based formal verification of SystemC
ACM Transactions on Embedded Computing Systems (TECS)
A framework for verification of software with time and probabilities
FORMATS'10 Proceedings of the 8th international conference on Formal modeling and analysis of timed systems
Lyrebird: assigning meanings to machines
SSV'10 Proceedings of the 5th international conference on Systems software verification
Concurrency-oriented verification and coverage of system-level designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic aspectization of systemC
Proceedings of the 2012 workshop on Modularity in Systems Software
Formal Analysis of SystemC Designs in Process Algebra
Fundamenta Informaticae
Verifying SystemC using an intermediate verification language and symbolic simulation
Proceedings of the 50th Annual Design Automation Conference
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation
Proceedings of the International Conference on Computer-Aided Design
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SystemC has emerged lately as a de facto, open, industry standard modeling language, enabling a wide range of modeling levels, from RTL to system level. Its increasing acceptance is driven by the increasing complexity of designs, pushing designers to higher and higher levels of abstractions. While a major goal of SystemC is to enable verification at higher level of abstraction, enabling early exploration of system-level designs, the focus so far has been on traditional dynamic validation techniques. It is fair to see that the development of formal-verification techniques for SystemC models is at its infancy. In spite of intensive recent activity in the development of formal-verification techniques for software, extending such techniques to SystemC is a formidable challenge. The difficulty stems from both the object-oriented nature of SystemC, which is fundamental to its modeling philosophy, and its sophisticated event-driven simulation semantics. In this position paper we discuss what is needed to develop formal techniques for SystemC verification, augmenting dynamic validation techniques. By formal techniques we refer here to a range of techniques, including assertion-based dynamic validation, symbolic simulation, formal test generation, explicit-state model checking, and symbolic model checking.