Formal verification of systemc designs using a petri-net based representation
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Constraint-Based Verification
Verification Methodology Manual for SystemVerilog
Verification Methodology Manual for SystemVerilog
Formal techniques for SystemC verification
Proceedings of the 44th annual Design Automation Conference
Formal verification at higher levels of abstraction
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Case study: Integrating FV and DV in the Verification of the Intel® Core^{TM} 2 Duo Microprocessor
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
Partial order reduction for scalable testing of systemC TLM designs
Proceedings of the 45th annual Design Automation Conference
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Model-driven automation for simulation-based functional verification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
An aspect-oriented, model-driven approach to functional hardware verification
Journal of Systems Architecture: the EUROMICRO Journal
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Abstract modeling has been widely used, albeit independently, for both formal verification and high-level modeling of SoC designs. In this paper we show that proper selection of modeling language and abstraction level can make the same code useful for both formal and simulation-based techniques. The abstract model enables architecture exploration and the development of verification collateral pre-RTL, and can be used as a behavioral checker in simulation against the RTL and in hardware emulation. In parallel, it enables applying formal verification techniques to verify the specification and implementation of the design. We provide examples of the successful application of abstract models developed in SystemVerilog in the course of the verification of the newest Intel® Core™ microprocessor.