Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Specifying Systems: The TLA+ Language and Tools for Hardware and Software Engineers
Experience with Applying Formal Methods to Protocol Specification and System Architecture
Formal Methods in System Design
Formal Verification of Square Root Algorithms
Formal Methods in System Design
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Formal Verification of the Pentium® 4 Floating-Point Multiplier
Proceedings of the conference on Design, automation and test in Europe
Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Shortening the verification cycle with synthesizable abstract models
Proceedings of the 46th Annual Design Automation Conference
Incremental modelling and verification of the PCI express transaction layer
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Incremental and verified modeling of the PCI express protocol
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
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During the recent development of a next-generation Intel processor, the project's formal verification team verified a new coherence protocol and portions of its RTL implementation against the protocol's specification within project deadlines. Typically, FV teams apply formal property verification (FPV) after RTL is coded and, though it continues to be an effective complement to pre-silicon validation, this late application prevents it from keeping pace with the continual complexity increases in hardware designs. Our discussion centers around how applying FV early in the development cycle of this processor enabled continual verification as the design progressed, culminating with the targeted RTL verification. We also present the languages and methodologies used, the reasons behind the choices, and where improvements can be made.