Experience with Applying Formal Methods to Protocol Specification and System Architecture

Authors:
Mani Azimi;Ching-Tsun Chou;Akhilesh Kumar;Victor W. Lee;Phamndra K. Mannava;Seungjoon Park
Affiliations:
Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA;Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA. ching-tsun.chou@intel.com;Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA;Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA;Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA;Intel Corporation, SC12-608, 3600 Juliette Lane, Santa Clara, CA 95054, USA
Venue:
Formal Methods in System Design
Year:
2003

Citing 9
Cited 2

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

IEEE Transactions on Computers
Formal verification by symbolic evaluation of partially-ordered trajectories

Formal Methods in System Design - Special issue on symbolic model checking
A formal proof of absence of deadlock for any acyclic network of PCI buses

CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Symbolic Model Checking

Symbolic Model Checking
A Survey of Wormhole Routing Techniques in Direct Networks

Computer
Practical Formal Verification in Microprocessor Design

IEEE Design & Test
Intel 870: A Building Block for Cost-Effective, Scalable Servers

IEEE Micro
A Compositional Rule for Hardware Design Refinement

CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification

Pre-RTL formal verification: an intel experience

Proceedings of the 45th annual Design Automation Conference
Extracting models from design documents with mapster

Proceedings of the twenty-seventh ACM symposium on Principles of distributed computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.