Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Computer Architecture; A Designer's Text Based on a Generic RISC
Computer Architecture; A Designer's Text Based on a Generic RISC
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
An error simulation based approach to measure error coverage of formal properties
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Experience with Applying Formal Methods to Protocol Specification and System Architecture
Formal Methods in System Design
Verifying the Implementation of an Error Control Code
Formal Methods in System Design
Overview of Hydra: A Concurrent Language for Synchronous Digital Circuit Design
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Laerte++: an object oriented high-level TPG for systemC designs
Languages for system specification
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
Functional formal verification on designs of pSeries microprocessors and communication subsystems
IBM Journal of Research and Development - POWER5 and packaging
Combining ACL2 and an automated verification tool to verify a multiplier
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A SAT-based procedure for verifying finite state machines in ACL2
ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
A MuDDy Experience---ML Bindings to a BDD Library
DSL '09 Proceedings of the IFIP TC 2 Working Conference on Domain-Specific Languages
A Semantic Condition for Data Independence and Applications in Hardware Verification
Electronic Notes in Theoretical Computer Science (ENTCS)
ICFEM'11 Proceedings of the 13th international conference on Formal methods and software engineering
A SAT-based decision procedure for the subclass of unrollable list formulas in ACL2 (SULFA)
IJCAR'06 Proceedings of the Third international joint conference on Automated Reasoning
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Practical application of formal methods requires more than advanced technology and tools;it requires an appropriate methodology. A verification methodology for data-path-dominated hardware combines model checking and theorem proving in a customizable framework. This methodology has been effective in large-scale industrial trials, including verification of an IEEE-compliant floating-point adder.