Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
PVS: Combining Specification, Proof Checking, and Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Model checking and theorem proving: a unified framework
Model checking and theorem proving: a unified framework
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
Proceedings of the conference on Design, automation and test in Europe - Volume 1
ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
Formalization of the DE2 language
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Combining Coq and Gappa for Certifying Floating-Point Programs
Calculemus '09/MKM '09 Proceedings of the 16th Symposium, 8th International Conference. Held as Part of CICM '09 on Intelligent Computer Mathematics
Multi-Prover verification of floating-point programs
IJCAR'10 Proceedings of the 5th international conference on Automated Reasoning
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We have extended the ACL2 theorem prover to automatically prove properties of VHDL circuits with IBM's Internal SixthSense verification system. We have used this extension to verify a multiplier used in an industrial floating point unit. The property we ultimately verify corresponds to the correctness of the component that produces a pair of bit-vectors whose summation is equal to the product. This property is beyond the scale of the SixthSense system alone. In this paper we show how we verified the multiplier by illustrating key ACL2 lemmas and theorems, and also properties checked by SixthSense.