Introduction to HOL: a theorem proving environment for higher order logic
Introduction to HOL: a theorem proving environment for higher order logic
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
ML for the working programmer (2nd ed.)
ML for the working programmer (2nd ed.)
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Writing testbenches: functional verification of HDL models
Writing testbenches: functional verification of HDL models
Introduction to Formal Hardware Verification: Methods and Tools for Designing Correct Circuits and Systems
Computer Architecture; A Designer's Text Based on a Generic RISC
Computer Architecture; A Designer's Text Based on a Generic RISC
The Formal Design of 1M-gate ASICs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Nuts and bolts of core and SoC verification
Proceedings of the 38th annual Design Automation Conference
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Tool Building Requirements for an API to First-Order Solvers
Electronic Notes in Theoretical Computer Science (ENTCS)
Accurate theorem proving for program verification
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
Explaining symbolic trajectory evaluation by giving it a faithful semantics
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Formalization of the DE2 language
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
| Hi-index | 0.00 |
We present a formal verification methodology for datapath-dominated hardware. This provides a systematic but flexible framework within which to organize the activities undertaken in large-scale verification efforts and to structure the associated code and proof-script artifacts. The methodology deploys a combination of model checking and lightweight theorem proving in higher-order logic, tightly integrated within a general-purpose functional programming language that allows the framework to be easily customized and also serves as a specification language. We illustrate the methodology--which has has proved highly effective in large-scale industrial trials--with the verification of an IEEE-compliant, extended precision floating-point adder.