Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
ML for the working programmer (2nd ed.)
ML for the working programmer (2nd ed.)
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Formal Verification of the Pentium® 4 Floating-Point Multiplier
Proceedings of the conference on Design, automation and test in Europe
A reflective functional language for hardware design and theorem proving
Journal of Functional Programming
Formal verification of high-level conformance with symbolic simulation
HLDVT '05 Proceedings of the High-Level Design Validation and Test Workshop, 2005. on Tenth IEEE International
Case study: Integrating FV and DV in the Verification of the Intel® Core^{TM} 2 Duo Microprocessor
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
Formal verification of hardware support for advanced encryption standard
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A Time-Optimal On-the-Fly Parallel Algorithm for Model Checking of Weak LTL Properties
ICFEM '09 Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Model checking a model checker: a code contract combined approach
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
Intel® Core™i7 processor execution engine validation in a functional language based formal framework
PADL'11 Proceedings of the 13th international conference on Practical aspects of declarative languages
vlogsl: a strategy language for simulation-based verification of hardware
HVC'10 Proceedings of the 6th international conference on Hardware and software: verification and testing
Verifying VIA Nano microprocessor components
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Timed automata approach to verification of systems with degradation
MEMICS'11 Proceedings of the 7th international conference on Mathematical and Engineering Methods in Computer Science
A model checking framework for hierarchical systems
ASE '11 Proceedings of the 2011 26th IEEE/ACM International Conference on Automated Software Engineering
Formal Methods in System Design
Refinement-Based modeling of 3d nocs
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
On-the-fly parallel model checking algorithm that is optimal for verification of weak LTL properties
Science of Computer Programming
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Formal verification of arithmetic datapaths has been part of the established methodology for most Intel processor designs over the last years, usually in the role of supplementing more traditional coverage oriented testing activities. For the recent Intel$^{\tiny\circledR}$ CoreTM i7 design we took a step further and used formal verification as the primary validation vehicle for the core execution cluster, the component responsible for the functional behaviour of all microinstructions. We applied symbolic simulation based formal verification techniques for full datapath, control and state validation for the cluster, and dropped coverage driven testing entirely. The project, involving some twenty person years of verification work, is one of the most ambitious formal verification efforts in the hardware industry to date. Our experiences show that under the right circumstances, full formal verification of a design component is a feasible, industrially viable and competitive validation approach.