Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Formal Verification of the VAMP Floating Point Unit
Formal Methods in System Design
FPgen - a test generation framework for datapath floating-point verification
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Formalization of fixed-point arithmetic in HOL
Formal Methods in System Design
Pre-RTL formal verification: an intel experience
Proceedings of the 45th annual Design Automation Conference
Formal verification of hardware support for advanced encryption standard
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
on the design of a formal debugger for system architecture
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Validating a modern microprocessor
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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We present the formal verification of the floating-point multiplier in the Intel IA-32 Pentium 炉 microprocessor. The verification is based on a combination of theorem-proving and BDD based model-checking tasks performed in a unified hardware verification environment. The tasks are tightly integrated to accomplish complete verification of the multiplier hardware coupled with the rounder logic. The approach does not rely on specialized representations like Binary Moment Diagrams or its variants.