Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
RTL verification: a floating-point multiplier
Computer-Aided reasoning
Computer Arithmetic Algorithms
Computer Arithmetic Algorithms
ML For the Working Programmer
ACM Transactions on Mathematical Software (TOMS)
Formal Verification of Square Root Algorithms
Formal Methods in System Design
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Formal Verification of Floating Point Trigonometric Functions
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Verification of Floating-Point Adders
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Formal Verification of the Pentium® 4 Floating-Point Multiplier
Proceedings of the conference on Design, automation and test in Europe
Automatic Formal Verification of Fused-Multiply-Add FPUs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
FM'05 Proceedings of the 2005 international conference on Formal Methods
Theorem Proving for Verification (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Formal verification of hardware support for advanced encryption standard
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Centaur Technology Media Unit Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Automatic verification of estimate functions with polynomials of bounded functions
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Hybrid verification of a hardware modular reduction engine
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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Commercial competition is forcing computer companies to get better products to market more rapidly, and therefore the time for validation is shrinking relative to the complexity of microprocessor designs. Improving time-to-market performance cannot be solved by just growing the size of design and validation teams. Design process automation is increasing, and the adoption of more rigorous methods, including formal verification, is unavoidable because for achieving the quality demanded by the marketplace. Intel is one of the strongest promoters of the use of formal methods across all phases of the design development. Intel's design teams use high-level modeling of protocols and algorithms, formal verification of floating-point libraries, design exploration systems based on formal methods, full proofs and property verification of RTL specifications, and equivalence checking to verify that transistor-level schematics correspond to their RTL specifications. Even with the best effort to adopt the progress in formal methods quickly, there is a large gap between an idea published at a conference and a development of a tool that can be used on industrial-sized designs. These tools and methods need to scale well, be stable during a multi-year design effort, and be able to support efficient debugging. The use of formal methods on a live design must allow for ongoing changes in the specification and the design. The methodology must be flexible enough to permit new design features, such as scan and power-down logic, soft error detection, etc. In this paper, I will share my experience with the formal verification of the floating-point unit on an Itanium(R) microprocessor design and point out how it may influence future microprocessor-design projects.