An Industrial Strength Theorem Prover for a Logic Based on Common Lisp
IEEE Transactions on Software Engineering
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Computer-Aided Reasoning: An Approach
Computer-Aided Reasoning: An Approach
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
An Integration of Model Checking with Automated Proof Checking
Proceedings of the 7th International Conference on Computer Aided Verification
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool
FMCAD '06 Proceedings of the Formal Methods in Computer Aided Design
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Automatic formal verification of block cipher implementations
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Formal verification of hardware support for advanced encryption standard
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
Automatic verification of estimate functions with polynomials of bounded functions
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Formalization of the DE2 language
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
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Wide-operand modular math functions pose an enormous challenge for verification. We present a novel method to verify a modular reduction engine implemented as a finite state machine (FSM), leveraging a combination of model checking and theorem proving. As a first step of the verification, preconditions and post-conditions for each state transition of the FSM are identified. Next the implications from the pre-conditions to the post-conditions are verified using a model checker. The last step entails combining all the implications in a theorem prover to derive the overall correctness proof. We carried out this verification using a hybrid formal verification platform comprising the ACL2 theorem prover and IBM's model checker SixthSense, along with numerous techniques to cope with the complexities of this verification task. To our knowledge, this is the first published method for the exhaustive verification of an RTL-implementation of a wide-operand industrial modular reduction engine.