Computer-aided verification of coordinating processes: the automata-theoretic approach
Computer-aided verification of coordinating processes: the automata-theoretic approach
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Checking Safety Properties Using Induction and a SAT-Solver
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
LICS '97 Proceedings of the 12th Annual IEEE Symposium on Logic in Computer Science
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists
Formal Methods in System Design
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor
Proceedings of the conference on Design, automation and test in Europe
Merging nodes under sequential observability
Proceedings of the 45th annual Design Automation Conference
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multi-clock SVA synthesis without re-writing
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Optimal constraint-preserving netlist simplification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Scalable liveness checking via property-preserving transformations
Proceedings of the Conference on Design, Automation and Test in Europe
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Approximate reachability with combined symbolic and ternary simulation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Hybrid verification of a hardware modular reduction engine
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
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A standard approach to improving circuit performance is to use an N-phase design style where combinational logic is interspersed freely between level sensitive latches controlled by separate clocks. Unfortunately, the use of an N-phase design style will increase the number of state variables by a factor of N, making formal verification many orders of magnitude harder. Previous approaches to solving this problem restrict the kind of designs that can be handled severely and construct an abstracted netlist with fewer state variables by a syntactic analysis that requires the user to identify clocks. We extend the current state of the art by introducing a phase abstraction algorithm that (1) poses no restrictions on the design style that can be used, that (2) avoids an error prone syntactic analysis, that (3) requires no input from users, and that (4) can be integrated into any model checker without requiring HDL code analysis.