Record & play: a structural fixed point iteration for sequential circuit verification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
AQUILA: An Equivalence Checking System for Large Sequential Designs
IEEE Transactions on Computers
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Formal property verification by abstraction refinement with formal, simulation and hybrid engines
Proceedings of the 38th annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Structural Symmetry and Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Recording synthesis history for sequential verification
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Retiming and Resynthesis: A Complexity Perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coping with Moore's law (and more): supporting arrays in state-of-the-art model checkers
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Large-scale application of formal verification: from fiction to fact
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Optimal redundancy removal without fixedpoint computation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Proving correctness of regular expression accelerators
Proceedings of the 49th Annual Design Automation Conference
Implicative simultaneous satisfiability and applications
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
Fast cone-of-influence computation and estimation in problems with multiple properties
Proceedings of the Conference on Design, Automation and Test in Europe
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The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inherent in redundancy identification hinges not only upon the ability to cross-assume those redundancies, but also upon the way in which these assumptions are leveraged. In this paper, we study the technique of speculative reduction for efficiently modeling redundancy assumptions. We provide theoretical and experimental evidence to demonstrate that speculative reduction is fundamental to the scalability of the redundancy identification process under various proof techniques. We also propose several techniques to speed up induction-based redundancy identification. Experiments demonstrate the effectiveness of our techniques in enabling substantially faster redundancy identification, up to six orders of magnitude on large designs.