Efficient latch optimization using exclusive sets
DAC '97 Proceedings of the 34th annual Design Automation Conference
A new retiming-based technology mapping algorithm for LUT-based FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Min-area retiming on flexible circuit structures
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
SAT-Based Verification without State Space Traversal
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
Exploiting suspected redundancy without proving it
Proceedings of the 42nd annual Design Automation Conference
Dynamic transition relation simplification for bounded property checking
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Automatic generalized phase abstraction for formal verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Inductive equivalence checking under retiming and resynthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Combinational and sequential mapping with priority cuts
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sequential equivalence checking based on structural similarities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming and Resynthesis: A Complexity Perspective
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Non-cycle-accurate sequential equivalence checking
Proceedings of the 46th Annual Design Automation Conference
Sequential logic synthesis using symbolic bi-decomposition
Proceedings of the Conference on Design, Automation and Test in Europe
Speculative reduction-based scalable redundancy identification
Proceedings of the Conference on Design, Automation and Test in Europe
Combinational techniques for sequential equivalence checking
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Scalable don't-care-based logic optimization and resynthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient implementation of property directed reachability
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Removing overhead from high-level interfaces
Proceedings of the 49th Annual Design Automation Conference
Microprocessors & Microsystems
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This paper describes an efficient implementation of sequential synthesis that uses induction to detect and merge sequentially-equivalent nodes. State-encoding, scan chains, and test vectors are essentially preserved. Moreover, the sequential synthesis results are sequentially verifiable using an independent inductive prover similar to that used for synthesis, with guaranteed completeness. Experiments with this sequential synthesis show effectiveness. When applied to a set of 20 industrial benchmarks ranging up to 26K registers and up to 53K 6-LUTs, average reductions in register and area are 12.9% and 13.1% respectively while delay is reduced by 1.4%. When applied to the largest academic benchmarks, an average reduction in both registers and area is more than 30%. The associated sequential verification is also scalable and runs about 2x slower than synthesis. The implementation is available in the synthesis and verification system ABC.