Boosting interpolation with dynamic localized abstraction and redundancy removal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Checking Safety by Inductive Generalization of Counterexamples to Induction
FMCAD '07 Proceedings of the Formal Methods in Computer Aided Design
Scalable and scalably-verifiable sequential synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Partitioning interpolant-based verification for effective unbounded model checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based model checking without unrolling
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
QuteRTL: towards an open source framework for RTL design synthesis and verification
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Generalized property directed reachability
SAT'12 Proceedings of the 15th international conference on Theory and Applications of Satisfiability Testing
Software model checking via IC3
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
Intertwined forward-backward reachability analysis using interpolants
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
QF BV model checking with property directed reachability
Proceedings of the Conference on Design, Automation and Test in Europe
A semi-canonical form for sequential AIGs
Proceedings of the Conference on Design, Automation and Test in Europe
Using cubes of non-state variables with property directed reachability
Proceedings of the Conference on Design, Automation and Test in Europe
GLA: gate-level abstraction revisited
Proceedings of the Conference on Design, Automation and Test in Europe
Core minimization in SAT-based abstraction
Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of feedback decoders for initialized encoders
Proceedings of the 50th Annual Design Automation Conference
A counterexample-guided interpolant generation algorithm for SAT-based model checking
Proceedings of the 50th Annual Design Automation Conference
Incremental, inductive coverability
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
Automatic abstraction in SMT-Based unbounded software model checking
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic model checking algorithm since Ken McMillan's interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm to study further. In this paper, we present a simplified and faster implementation of Bradley's procedure, and discuss our successful and unsuccessful attempts to improve it.