QuteRTL: towards an open source framework for RTL design synthesis and verification

Authors:
Hu-Hsi Yeh;Cheng-Yin Wu;Chung-Yang (Ric) Huang
Affiliations:
Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan
Venue:
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Year:
2012

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Abstract

We build an open-source RTL framework, QuteRTL, which can serve as a front-end for research in RTL synthesis and verification. Users can use QuteRTL to read in RTL Verilog designs, obtain CDFGs, generate hierarchical or flattened gate-level netlist, and link to logic synthesis/optimization tools (e.g. Berkeley ABC). We have tested QuteRTL on various RTL designs and applied formal equivalence checking with third party tool to verify the correctness of the generated netlist. In addition, we also define interfaces for the netlist creation and formal engines. Users can easily adopt other parsers into QuteRTL by the netlist creation interface, or call different formal engines for verification and debugging by the formal engine interface. Various research opportunities are made possible by this framework, such as RTL debugging, word-level formal engines, design abstraction, and a complete RTL-to-gate tool chain, etc. In this paper, we demonstrate the applications of QuteRTL on constrained random simulation and property checking.