Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Constructive library-aware synthesis using symmetries
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Structural Detection of Symmetries in Boolean Functions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Proceedings of the 43rd annual Design Automation Conference
Postplacement rewiring by exhaustive search for functional symmetries
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Faster symmetry discovery using sparsity of symmetries
Proceedings of the 45th annual Design Automation Conference
Effective preprocessing in SAT through variable and clause elimination
SAT'05 Proceedings of the 8th international conference on Theory and Applications of Satisfiability Testing
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient implementation of property directed reachability
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Symmetry and satisfiability: an update
SAT'10 Proceedings of the 13th international conference on Theory and Applications of Satisfiability Testing
Conflict anticipation in the search for graph automorphisms
LPAR'12 Proceedings of the 18th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Solving difficult instances of Boolean satisfiability in the presence of symmetry
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast computation of symmetries in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In numerous EDA flows, time-consuming computations are repeatedly applied to sequential circuits. This motivates developing methods to determine what circuits have been processed already by a tool. This paper proposes an algorithm for semi-canonical labeling of nodes in a sequential AIG, allowing problems or sub-problems solved by an EDA tool to be cached with their computed results. This can speed up the tool when applied to designs with isomorphic components or design suites exhibiting substantial structural similarity.