Symmetry detection and dynamic variable ordering of decision diagrams
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Generalized Reed-Muller Forms as a Tool to Detect Symmetries
IEEE Transactions on Computers
Better verification through symmetry
Formal Methods in System Design - Special issue on symmetry in automatic verification
Formal Methods in System Design - Special issue on symmetry in automatic verification
Detection of symmetry of Boolean functions represented by ROBDDs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Fast post-placement rewiring using easily detectable functional symmetries
Proceedings of the 37th Annual Design Automation Conference
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Generalized symmetries in boolean functions
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Limits of Using Signatures for Permutation Independent Boolean Comparison
Formal Methods in System Design
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases
Proceedings of the 40th annual Design Automation Conference
Constructive multi-level synthesis by way of functional properties
Constructive multi-level synthesis by way of functional properties
Structural Detection of Symmetries in Boolean Functions
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Efficient translation of boolean formulas to CNF in formal verification of microprocessors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
ShatterPB: symmetry-breaking for pseudo-Boolean formulas
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Circuit SAT Solver With Signal Correlation Guided Learning
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
K-disjointness paradigm with application to symmetry detection for incompletely specified functions
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
Proceedings of the 43rd annual Design Automation Conference
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Solving difficult instances of Boolean satisfiability in the presence of symmetry
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast computation of symmetries in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using simulation and satisfiability to compute flexibilities in Boolean networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Linear cofactor relationships in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to combinational equivalence checking
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A semi-canonical form for sequential AIGs
Proceedings of the Conference on Design, Automation and Test in Europe
Generalized Boolean symmetries through nested partition refinement
Proceedings of the International Conference on Computer-Aided Design
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Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-based method that makes uses of structural analysis, integrated simulation and Boolean satisfiability for fast and scalable detection of classical symmetries of completely-specified Boolean functions. This is in contrast to previous incomplete circuit-based methods and complete BDD-based methods. Experimental results demonstrate that the proposed method works for large Boolean functions, for which BDDs cannot be constructed.