Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Star test: the theory and its applications
Star test: the theory and its applications
In-place delay constrained power optimization using functional symmetries
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Layout-driven hot-carrier degradation minimization using logic restructuring techniques
Proceedings of the 38th annual Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ATPG-based logic synthesis: an overview
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
Proceedings of the 2008 international symposium on Physical design
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
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Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear time algorithm is proposed to detect functional symmetries in the Boolean network and is used as the basis for rewiring. Integration with an existing gate sizing algorithm further proves the effectiveness of our technique. Experimental results are very promising.