In-place delay constrained power optimization using functional symmetries

A survey of power estimation techniques in VLSI circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design

POSE: power optimization and synthesis environment

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Reducing power dissipation after technology mapping by structural transformations

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Post-layout logic restructuring for performance optimization

DAC '97 Proceedings of the 34th annual Design Automation Conference

Gate sizing for constrained delay/power/area optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design

Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction

ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design

Power reduction and power-delay trade-offs using logic transformations

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Fast post-placement rewiring using easily detectable functional symmetries

Proceedings of the 37th Annual Design Automation Conference

STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs

ITC '99 Proceedings of the 1999 IEEE International Test Conference