A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A formal non-heuristic ATPG approach
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing
IEEE Transactions on Computers
STARBIST: scan autocorrelated random pattern generation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Scan-Encoded Test Pattern Generation for BIST
Proceedings of the IEEE International Test Conference
Robust Search Algorithms for Test Pattern Generation
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
PODEM-X: An automatic test generation system for VLSI logic structures
DAC '81 Proceedings of the 18th Design Automation Conference
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A scheduling problem in test generation
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
The Complexity of Fault Detection Problems for Combinational Logic Circuits
IEEE Transactions on Computers
Fault Equivalence in Combinational Logic Networks
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational test generation using satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
In-place delay constrained power optimization using functional symmetries
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Layout-driven hot-carrier degradation minimization using logic restructuring techniques
Proceedings of the 38th annual Design Automation Conference
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Star test is a novel test pattern generation technique inwhich a few test vectors serve as centers of clusters for othertest vectors which are derived by complementing at randomtheir coordinates. By properly selecting the deterministicpatterns as centers, the star tests have very high probabilityto detect most of the faults in a circuit. This paper presentsan efficient algorithm to combine the star test approach witha traditional test pattern generator yielding a significantspeed up of the ATPG process. With the new STAR-ATPGmethodology, the major effort of the test generation is transferredfrom an computationally more complex test patterngeneration process into simpler fault simulation. Experimentalresults on several large industrial designs demonstratethat a factor of 1.5-2.5 average speed up is achieved by thenew method with the same abort limit. Also, STAR-ATPGachieves higher fault coverage than traditional ATPG underthe same abort limit. To achieve the same fault coverage asSTAR-ATPG, it requires the traditional method to increasethe abort limit significantly and result in 5 times slower.